Time varying data permutation apparatus and methods

ABSTRACT

Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.

This application is a continuation of U.S. patent application Ser. No. 14/066,332 filed on Oct. 29, 2013, which is a continuation of U.S. patent application Ser. No. 13/190,194 filed on Jul. 25, 2011, the contents of each of which are incorporated in their entirety herein by reference.

FIELD OF THE INVENTION

Field of the Invention

This invention relates generally to error correction coding and, in particular, to permuting data for error decorrelation.

Background

Most Forward-Error-Correction (FEC) codes are designed to perform under Additive White Gaussian Noise (AWGN). That is, a decoder assumes that noise samples in a received signal are uncorrelated and Gaussian distributed. The performance of these codes can substantially decrease if the noise that is added during transmission over a communication channel is actually correlated. Error decorrelators can be added to a FEC encoder and decoder to reduce the correlation of noise samples and the resultant data errors, so that coding performance can approach performance under AWGN conditions.

The memory size or depth that is required for data permutation in a conventional error decorrelator increases with the degree of correlation, since decorrelation of errors due to more highly correlated noise involves permutation of larger amounts of data and storage of that data in memory to enable the permutation. In general, the complexity of a conventional error decorrelator is linearly proportional to the throughput of data to be permuted, and is further proportional to the square of the memory depth. Complexity might refer to gate count and/or memory size in hardware, or to code size, code speed, and/or memory footprint of a function in software or firmware, for example. The linear proportionality of complexity to data throughput can be particularly problematic for high-speed communication channels operating at about 40 Gigabits per second (Gbps) and above, for instance.

BRIEF DESCRIPTION OF THE DRAWINGS

Examples of embodiments of the invention will now be described in greater detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of an example FEC system with error decorrelation.

FIG. 2 is a block diagram of another example FEC system with error decorrelation.

FIG. 3 is a block diagram of an example permutation apparatus.

FIG. 3A is a block diagram of an example data encoder.

FIG. 4 is a block diagram of an example permutation element.

FIG. 5 is a block diagram of another example permutation apparatus.

FIG. 6 is a block diagram of an example FEC system in an Optical Transport Network (OTN) application.

FIG. 7 is a flow diagram illustrating an example data permutation method.

DETAILED DESCRIPTION

The complexity of an error decorrelator is reduced by splitting data permutation into multiple permutation operations in respective different dimensions. The multiple permutation operations in multiple dimensions provide an overall effective data permutation using smaller blocks in each permutation than would be required to achieve the same degree of permutation in a classical error decorrelator design. The dimension of permutation is changed between permutation operations by interleaving data that is permuted in one permutation operation, and then permuting the interleaved permuted data in a subsequent permuting operation.

Permutation of smaller blocks of data can significantly reduce gate count and complexity as compared to a classical design that achieves the same overall degree of data permutation.

FIG. 1 is a block diagram of an example FEC system 100 with error decorrelation. The example FEC system 100 includes a transmitter 102 and a receiver 104 which communicate via a communication channel 106. The communication channel could be an optical channel or some other type of channel. The transmitter 102 includes a data generator 110, a decorrelator interleaver 112, a systematic FEC encoder 114, and a decorrelator de-interleaver 116. The receiver 104 includes a data receiver 120, a decorrelator interleaver 122, a systematic FEC decoder 124, and a decorrelator de-interleaver 126.

A complete communication system might include many transmitters and receivers which use the same or different communication channels. Equipment in which or in conjunction with which the example transmitter 102 and receiver 104 are implemented could also include other components which have not been shown in FIG. 1 in order to avoid congestion in the drawing. It should therefore be appreciated that the example FEC system 100 of FIG. 1, as well as the contents of the other drawings, are intended solely for illustrative purposes, and that the present disclosure is in no way limited to the particular examples explicitly shown in the drawings.

The components of the transmitter 102 and the receiver 104 are operatively coupled together as shown. Components could be operatively coupled together through electrical, optical, and/or other types of connections, which might be direct connections as shown or indirect connections through one or more other components. Operative couplings could also or instead include non-physical connections such as logical connections between components implemented using elements that execute software. An operative coupling between such components could be in the form of shared or commonly accessed memory or register locations, for instance.

The data generator 110 is intended to represent a source of data. The data source could be part of the transmitter 102, or the data generator 110 might also or instead receive data from one or more external sources for transmission over the communication channel 106. The form of implementation of the data generator 110 might vary, for instance, depending on the type(s) of data to be handled, whether the data generator directly generates data or receives data from an external source, and/or other data handling features that are to be provided at the transmitter 102. In an example discussed in further detail below with reference to FIG. 6, the data generator 110 is implemented in the form of a frame generator which generates blocks of data in a certain frame format but need not necessarily directly generate data.

Examples of possible implementations of the data generator 110 include hardware, firmware, one or more processors executing software stored in computer-readable storage, or some combination thereof. Application Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), and microprocessors for executing software stored on a non-transitory computer-readable medium such as a magnetic or optical disk or a solid state memory device, are examples of devices that might be suitable for implementing the data generator 110. Any or all of the other components of the transmitter 102, and similarly the receiver 104, could also be implemented in any of various ways.

The decorrelator interleavers 112, 122 at the transmitter 102 and the receiver 104 apply the same multi-dimensional data permutation to their input data streams, before FEC encoding and decoding, respectively. The FEC encoder 114 and the FEC decoder 124 employ systematic coding in the example FEC system 100. Systematic coding adds coding information to data rather than changing any data. The decorrelator de-interleavers 116, 126 implement the inverse permutations of the decorrelator interleavers 112, 122, respectively. This means that the sequence of data at the output of each decorrelator de-interleaver 116, 126 is the same as the sequence of data at the input of its corresponding decorrelator interleaver 112, 122. The decorrelator interleavers 112, 122 reorder data, and the decorrelator de-interleavers 116, 126 reverse that reordering to restore the original order of a data stream that is generated by the data generator 110 in the case of the transmitter 102 or a data stream that is received from the communication channel 106 in the case of the receiver 104.

The data receiver 120 in the example FEC system 100 could implement such receiver operations as equalization and data frame recovery, for example. In some embodiments, the data receiver 120 is a “protocol” counterpart of the data generator 110, such that a particular protocol runs between the data generator and the data receiver.

For systematic FEC coding, the decorrelator interleavers 112, 122 are designed in such a way that data locations are not mixed with systematic FEC parity locations. This allows the error decorrelation to be somewhat independent of the particular FEC code structure, apart from not mixing the data and parity locations, and makes the error decorrelation “transparent” to the systematic FEC encoder and decoder 114, 124.

In a non-systematic FEC system, it is possible to remove one decorrelator interleaver and one decorrelator de-interleaver to reduce the overall system complexity. This is shown in FIG. 2, which is a block diagram of another example FEC system with error decorrelation. The example FEC system 200 is substantially similar to the example FEC system 100 in FIG. 1, and includes a transmitter 202 with a data generator 210 and a decorrelator de-interleaver 216, a receiver 204 with a data receiver 220 and a decorrelator interleaver 222, and a channel 206. In the example FEC system 200, however, the FEC encoder and decoder 214, 224 are non-systematic, and there are no permutations at the input of the FEC encoder and the output of the FEC decoder. The decorrelator de-interleaver 216 and the decorrelator interleaver 222 apply inverse data permutations, to enable decorrelation of errors due to noise affecting the communication channel 206.

It should be appreciated that the designation of decorrelator components as decorrelator interleaver and decorrelator de-interleaver is arbitrary. A decorrelator interleaver and a corresponding decorrelator de-interleaver implement inverse overall data reordering, and either component could be designated as the decorrelator interleaver or as the decorrelator de-interleaver. Thus, the decorrelator de-interleaver 216 could be switched with the decorrelator interleaver 222. This also applies to the example FEC system 100 of FIG. 1 as well. In general, each decorrelator interleaver 112, 122 could be replaced with it corresponding decorrelator de-interleaver 116, 126, provided each decorrelator de-interleaver is also replaced with its corresponding decorrelator interleaver.

Another difference between the example FEC systems 100, 200 in FIGS. 1 and 2 is that the error decorrelation in FIG. 1 is protocol transparent. Where the data generator 110 in FIG. 1 generates frames in accordance with a particular protocol, for example, the output of the decorrelator de-interleaver 116 is also framed in accordance with the same protocol. In the example FEC system 200, however, permutation by the decorrelator de-interleaver 216 would change the order of data in an encoded data stream, and therefore this reordering would not be transparent to a protocol between the data generator 210 and the data receiver 220. The error decorrelation is still transparent to the FEC encoder and decoder 214, 224, but not to the data receiver 220.

FIG. 3 is a block diagram of an example permutation apparatus 300. The example permutation apparatus 300 could be used to implement the decorrelator interleavers in the example FEC systems 100, 200 in FIGS. 1 and 2, for instance. In the example permutation apparatus 300, a first time varying permutation element 302 is operatively coupled to receive an input data stream D_(in), a block interleaver 304 is operatively coupled to an output of the first time varying permutation element, and a second time varying permutation element 306 is operatively coupled to an output of the block interleaver 304 and provides an output data stream D_(out). In operation, the first time varying permutation element 302 applies a time varying first permutation to the input data stream D_(in) to generate a first permuted data stream, the block interleaver 304 interleaves the first permuted data stream to generate an interleaved data stream, and the second time varying permutation element 306 applies a time varying second permutation to the interleaved data stream to generate a second permuted data stream.

The same type of structure as shown in FIG. 3 can also be used in implementing decorrelation de-interleavers, with the exception that the block interleaver 304 would be replaced with a block de-interleaver implementing the inverse of interleaving that is applied by a block interleaver in a decorrelator interleaver, and the time varying permutation elements 302 and 306 would implement the inverses of permutations applied by time varying permutation elements in the decorrelator interleaver.

Generally, the complexity of a time varying decorrelator interleaver or de-interleaver is proportional to the square of the interleaving depth. This makes large interleaver designs very inefficient. The example permutation apparatus 300, however, is partitioned into the three elements as shown, including the two time varying permutation elements 302, 306 and the block interleaver 304, which reduces complexity as discussed below.

Regarding complexity of the example permutation apparatus 300, suppose that the time varying permutation elements 302, 306 respectively apply length n time varying permutations P1 and P2, and that the block interleaver 304 applies a permutation on n by m elements. Proceeding from the input at D_(in) to the output at D_(out), data is first permuted by P1, then permuted by interleaving at the block interleaver 304 and finally is permuted by P2. This results in an overall n*m time varying permutation. The complexity of implementation of P1 and P2 is proportional to n². This should be compared with the complexity of direct implementation of a time varying n*m permutation, which is m²*n². This means that a permutation apparatus of the form shown in FIG. 3 can result in substantial complexity reduction relative to a classical design for the same degree or level of data permutation.

The depth of the overall permutation can be chosen as a function of the error correlation length and the FEC code crossover probability of the particular FEC code in conjunction with which error decorrelation is to be implemented. As the permutation depth gets larger, noise at the output more closely approximates an uncorrelated source.

In an error decorrelation application, the example permutation apparatus 300 could be implemented in a data encoder that includes an encoder to encode a data stream to generate an encoded data stream. The first permutation element 302 could be operatively coupled to the encoder to apply a time varying first permutation to the encoded data stream.

FIG. 3A is a block diagram of an example data encoder having this type of structure at the output of an encoder. The example data encoder 350 includes a first permutation apparatus 360, a FEC encoder 370, and a second permutation apparatus 380. Each of the first and second permutation apparatus 360, 380 includes a time varying permutation element 362, 382 operatively coupled to a block interleaver 364 or a block de-interleaver 384, which is operatively coupled to another time varying permutation element 366, 386. In this example data encoder 350, the FEC encoder 370 encodes a data stream, and the time varying permutation element 382 is operatively coupled to the encoder to apply a time varying permutation to the encoded data stream that is output by the FEC encoder.

The example data encoder 350 provides for protocol transparency, since the permutation apparatus 360, 380 implement a decorrelator interleaver and a decorrelator de-interleaver, respectively. The FEC encoder 370 is operatively coupled to the second time varying permutation element 366 of the permutation apparatus 360, to receive and encode the second permuted data stream to generate an encoded data stream at the FEC encoder output. The second permutation apparatus 380 includes a third time varying permutation element 382 operatively coupled to the FEC encoder 370 to apply to the encoded data stream at the output of the FEC encoder, a time varying third permutation which is an inverse permutation of the time varying second permutation applied by the second permutation element 366. This generates a third permuted data stream, which in this example is then provided to a block de-interleaver 384. The block de-interleaver 384 de-interleaves the third permuted data stream from the third time varying permutation element 382 to generate a de-interleaved data stream. De-interleaving applied by the block de-interleaver 384 is an inverse of interleaving applied by the block interleaver 364. The de-interleaved data stream is in turn provided to a fourth time varying permutation element 386. The fourth time varying permutation element applies a time varying fourth permutation to the de-interleaved data stream from the block de-interleaver 384. The time varying fourth permutation is an inverse permutation of the time varying first permutation applied by the time varying permutation element 362.

An architecture of the form shown in FIG. 3A could also be implemented in a data decoder, with or without protocol transparency. In a data decoder implementation, the FEC encoder 370 would be replaced with a FEC decoder, and the data stream D_(in) would be an encoded data stream. The data decoder would include the FEC decoder operatively coupled to the second time varying permutation element 366 to receive and decode the second permuted data stream. For protocol transparency, the third time varying permutation element 382 could be operatively coupled to the FEC decoder to apply a time varying third permutation to the decoded data stream at the output of the FEC decoder to generate a third permuted data stream, with the time varying third permutation being an inverse permutation of the time varying second permutation that is applied by the second time varying permutation element 366. The block de-interleaver 384 then de-interleaves the third permuted data stream from the third time varying permutation element 382 by applying de-interleaving that is an inverse of interleaving applied by the block interleaver 364, to generate a de-interleaved data stream, and the fourth time varying permutation element 386 applies a time varying fourth permutation to the de-interleaved data stream at the output of the block de-interleaver 384. The time varying fourth permutation is an inverse permutation of the time varying first permutation applied by the time varying permutation element 362.

A protocol transparent data coding system could include both a data encoder and a data decoder that provide protocol transparency, with data permutation at the input and the output of both an encoder and a decoder. Where protocol transparency is provided, each of a data encoder and a data decoder could have an architecture of the form shown in FIG. 3A. In this case, there would be two decorrelator interleavers (one at the data encoder and one at the data decoder) and two decorrelator de-interleavers (one at the data encoder and one at the data decoder), each having four time varying permutation elements as shown at 362, 366, 382, 386, a block interleaver as shown at 364, and a block de-interleaver as shown at 384. Thus, between the data encoder and the data decoder, there would be a total of eight time varying permutation elements (four at the data encoder and four at the data decoder), two block interleavers (one at the data encoder and one at the data decoder), and two block de-interleavers (one at the data encoder and one at the data decoder). Time varying permutations applied by the time varying permutation elements at the data decoder would match those applied by the corresponding time varying permutation elements at the data encoder. Similarly, interleaving and de-interleaving applied by the block interleaver and the block de-interleaver at the data decoder would match the interleaving and de-interleaving applied by the block interleaver and the block de-interleaver at the data decoder.

In a data coding system without protocol transparency, data permutation would instead be applied only after the output of an encoder and before the input of a decoder. With reference to FIG. 3A, a data encoder might then include the FEC encoder 370 and the permutation apparatus 380 as a decorrelator de-interleaver, with a data decoder including the permutation apparatus 360 as a decorrelator interleaver operatively coupled to a FEC decoder, for example.

FIG. 4 is a block diagram of an example permutation element 400, which could be used to implement the time varying permutation elements 302, 306 in the example permutation apparatus 300 shown in FIG. 3 and/or the time varying permutation elements 362, 366, 382, 386 shown in FIG. 3A. The example permutation element 400 includes a multiple-stage permutation element 402 and a controller 405. The multiple-stage permutation element 402 includes a serial cascade of r permutation stages 410, 420, 430, 440, 450. At each ith permutation stage 410, 420, 430, 440, 450, the controller 405 controls a selection between one of two permutation maps π_(i1), π_(i2), each of which provides a respective different mapping between data positions or locations in an input data stream and a permuted (output) data stream. The controller 405 dynamically changes signals on the select lines, resulting in a time varying permutation. The permutation maps π_(i1), π_(i2) at each permutation stage 410, 420, 430, 440, 450 can be chosen to achieve a desired level of “pseudo-randomness” in the resultant r-stage permutation.

Not every permutation map π_(i1), π_(i2) need necessarily be random. For example, all π_(i1) could be set to identity I and all π_(i2) could be set to respective pseudo-random maps. In this type of implementation, each permutation stage 410, 420, 430, 440, 450 could be individually turned “off” by selecting the identity permutation map π_(i1) or turned “on” by selecting the pseudo-random map π_(i2).

A very simple algorithm could potentially be used by the controller 405 to control permutation map selection at each permutation stage 410, 420, 430, 440, 450. For example, a binary counter counting from 0 to 2^(r)−1 could be implemented as the controller 405 to provide a time varying r-bit control signal and thus a time varying r-stage permutation. The binary counter in this example could be driven by the same reference clock that is used to clock one or more other components for instance, such that the time varying r-stage permutation at each permutation stage 410, 420, 430, 440, 450 changes for each clock cycle. Other embodiments could use more slowly or more quickly varying permutations. The actual selection at each stage could be implemented using a switch, multiplexer, or some other form of selector.

A permutation element of the form shown in FIG. 4 could be used to implement each of multiple permutations in a permutation apparatus. Control signals for each permutation, in a control pair (p1_control, p2_control) where there are two permutations P1, P2, for instance, could be generated independently, so as to increase the number of possible combinations of different overall pseudo-random permutations that could be applied by a permutation apparatus over time. Each of first and second permutation elements in this example would include a respective set of serially coupled permutation stages.

With reference to FIG. 1, within the transmitter 102, for example, time varying permutations applied at the decorrelator interleaver 112 and the decorrelator de-interleaver 116 are coordinated so that the decorrelator de-interleaver can apply the inverse of the time varying permutation that was applied at the decorrelator interleaver. Where the decorrelator interleaver 112 and the decorrelator de-interleaver 116 include permutation elements having a structure as shown in FIG. 4, this type of coordination involves coordination of control signals that are supplied to the de-interleaver with those that are supplied to the interleaver, so that data to which a particular permutation is applied also has the correct inverse permutation applied. At the receiver 104, control signals within the decorrelator interleaver 122 and the decorrelator de-interleaver 126 are similarly coordinated.

Coordination of transmit-side permutations with receive-side permutations is also provided in systems which support protocol transparency. With reference again to FIG. 1, the decorrelator interleavers 112, 122 apply the same permutations, and the decorrelator de-interleavers 116, 126 apply the same inverse permutations. In a synchronized data system, the same synchronization mechanism that is used to synchronize the data could also be used to coordinate permutation control signals. Where the controller 405 is implemented using a counter, for example, control signals could be coordinated by synchronizing the counters at the decorrelator interleavers 112, 122 and the decorrelator de-interleavers 116, 126 based on data synchronization.

In FIG. 4, all of the permutation stages 410, 420, 430, 440, 450 are controllable. Time varying permutations could be provided with at least one controllable permutation stage, but not every permutation stage need necessarily be implemented as a controllable stage. Each controllable permutation stage is controllable to select, from different permutation maps, a respective permutation map to be applied by that controllable permutation stage. Fixed stages, if any, apply fixed permutation maps. In combination with one or more controllable permutation stages, even fixed permutation stages could be used to provide an overall time varying permutation.

It should also be noted that any or all permutation stages 410, 420, 430, 440, 450 could provide more than two permutation maps. Selection between more than two maps could be supported by providing multi-bit binary select signals, for example.

FIG. 4 and the corresponding description thereof relate to an example permutation element. Regarding block interleavers and block de-interleavers, a fixed map or several fixed maps for permuting a data stream in multiple dimensions could be used. A matrix transpose, for example, could be used to interleave/de-interleave a permuted data stream generated by a permutation element. Where a block interleaver/de-interleaver implements several maps, the block interleaver/de-interleaver could also be coupled to a controller. An interleaver controller could be the same controller 405 (FIG. 4) that controls selections between permutation maps, or possibly a separate controller.

FIG. 5 is a block diagram of another example permutation apparatus 500, which includes two permutation elements 502, 506 that could each be implemented as shown in FIG. 4 to apply respective 64-bit time varying permutations under control of the controller 505, and a 64-bit by 64-bit block interleaver 504, which could be implemented using one or more memory devices. In this example permutation apparatus 500, a 64-bit data stream is received by the permutation element 502, which applies a 64-bit time varying permutation to the data stream and fills the 64-bit by 64-bit block interleaver 504 row-by-row. This 64-bit by 64-bit block of data is then read column-by-column and passed through a second 64-bit time-varying permutation, which is applied by the permutation element 506. The controller 505 controls the selection of the permutation maps to be applied by the permutation elements 502, 506.

The example permutation apparatus 500, with two 64-bit permutations and a 64-bit by 64-bit matrix transpose for the block interleaver 504, provides an overall permutation depth of n*m=64*64=4096 bits. Complexity of the time varying permutation elements is proportional to n²=64², instead of (n*m)²=4096² as in a classical design to achieve a permutation depth of 4096 bits.

The present disclosure is not in any way limited to the example permutation apparatus 500 as shown in FIG. 5. In another embodiment, data permutation is applied to a 100 Gbps data stream using a two-dimensional block interleaver and 320-bit time varying permutations P1 and P2. Other embodiments are also possible.

FIG. 6 is a block diagram of an example FEC system in an Optical Transport Network (OTN) application. In the example FEC system 600, a transmitter 602 and a receiver 604 communicate through an optical communication channel 606. The transmitter 602 and the receiver 604 are similar in structure to the transmitter 102 and the receiver 104 in the example FEC system 100 (FIG. 1), but are specific to an OTN application. Thus, the transmitter 602 includes an Optical channel Transport Unit (OTUk) frame generator 610 as an example of a data receiver, an OTUk row interleaver 612 and de-interleaver 616 as examples of a decorrelator interleaver and de-interleaver, and a FEC encoder 614. At the receiver 604, the OTUk framer 620 which recovers OTUk frames from signals received over the optical channel 606, is an example of a data receiver. The OTUk row interleaver 622 and the OTUk row de-interleaver 626 represent examples of a receive side decorrelator interleaver and de-interleaver. The receiver 604 also includes a FEC decoder 624.

OTUk signals are defined in Recommendation G.709/Y.1331 by the Telecommunication Standardization section of the ITU (ITU-T), entitled “Interfaces for the Optical Transport Network (OTN)”, December 2009, with an Erratum 1 (May 2010), an Amendment 1 (July 2010), and a Corrigendum 1 (July 2010). G.709 defines a number of layers in an OTN signal hierarchy. Client signals are encapsulated into Optical channel Payload Unit (OPUk) signals at one of k levels of the OTN signal hierarchy. An Optical channel Data Unit (ODUk) carries the OPUk and supports additional functions such as monitoring and protection switching. OTUk adds FEC coding. Optical Channel (OCh) signals in G.709 are in the optical domain, and result from converting OTUk signals from electrical form to optical form. Further details on OTUk signals can be found in G.709.

One option to make data permutation for error decorrelation as disclosed herein compatible with the OTN OTUk row format is to design the overall permutations as follows:

-   -   a 12-stage 64-bit permutation for each of first and second         permutations P1 and P2;     -   a 40-bit by 64-bit=2560-bit matrix transpose function for block         interleaving between P1 and P2 for the first 11 blocks of 2560         bits of data;     -   a 38-bit by 64-bit=2432-bit matrix transpose function for block         interleaving between P1 and P2 for the 12th block of data, which         is the last block of data in an OTUk row;     -   a 32-bit by 64-bit=2048-bit matrix transpose function for block         interleaving between P1 and P2 for the 13th block, which         includes parity bits in an OTUk row.

Note that 11×2560+2432=30592 bits, which is the size of the data block in an OTUk row, and there are 2048 bits in an OTUk row. With the above set of block interleaving maps, the data and parity bits are not mixed.

To control P1 and P2 in this example, binary counters p1_cnt and p2_cnt could be used, with p1_cnt varying from 1 to 4095 and p2_cnt varying from 1 to (4095−41). Since the number 41 is prime, the pair (p1_cnt, p2_cnt) will traverse a large number of combinations before wrap around.

To synchronize the state of the controllers between the receiver and the transmitter, the OTUk MFAS byte can be used. For example, (p1_cnt, p2_cnt) could be forced to (1,1) every time MFAS=0. Since MFAS is an 8-bit value, the total distinct number of control pairs is 256×4×32640/64=522,240, which is a large number resulting in a good overall randomization of permutations for the error decorrelation.

FIG. 7 is a flow diagram illustrating an example data permutation method. The example data permutation method 700 involves applying a time varying first permutation to a data stream to generate a first permuted data stream at 702, interleaving the first permuted data stream to generate an interleaved data stream at 704, and applying a time varying second permutation to the interleaved data stream to generate a second permuted data stream at 706.

The example data permutation method 700 is intended solely for illustrative purposes. Variations are contemplated.

For example, the applying operations at 702, 706 might involve selecting, from multiple different permutation maps, at least one respective permutation map to be applied in each operation. Additional operations such as encoding and/or decoding, possibly in combination with further applying/interleaving/applying cycles to provide for protocol transparency, could be performed in some embodiments. Further variations might be or become apparent to a skilled person, based on FIGS. 1 to 6 and the foregoing description thereof, for instance.

What has been described is merely illustrative of the application of principles of embodiments of the invention. Other arrangements and methods can be implemented by those skilled in the art without departing from the scope of the present invention.

For example, the divisions of functions shown in FIGS. 1 to 6 are intended solely for illustrative purposes.

In addition, although described primarily in the context of methods and systems, other implementations are also contemplated, as a non-transitory computer-readable medium storing instructions executable by a machine, for example. 

We claim:
 1. A Forward Error Correction (FEC) coding system comprising: a FEC coding device; a first error decorrelator, operatively coupled to the FEC coding device, to apply multiple permutation operations to an encoded data stream in respective different dimensions; and a second error decorrelator to apply multiple permutation operations to a data stream in respective different dimensions to generate a permuted data stream, the FEC coding device comprising an encoder operatively coupled to the second error decorrelator to receive and encode the permuted data stream from the second error decorrelator to generate the encoded data stream, the multiple permutation operations of the first error decorrelator being inverses of the multiple permutation operations of the second error decorrelator, the FEC coding system further comprising: a third error decorrelator operatively coupled to the first error decorrelator to apply multiple permutation operations in respective dimensions to a permuted encoded data stream from the first error decorrelator, the multiple permutation operations of the third error decorrelator matching the multiple permutation operations of the second error decorrelator; a decoder operatively coupled to the third error decorrelator to decode a permuted data stream from the third error decorrelator to generate a decoded data stream; a fourth error decorrelator operatively coupled to the decoder to apply multiple permutation operations in respective dimensions to the decoded data stream, the multiple permutation operations of the fourth error decorrelator matching the multiple permutation operations of the first error decorrelator.
 2. The FEC coding system of claim 1, the first error decorrelator comprising: a first permutation element to apply a time varying first permutation to the encoded data stream to generate a first permuted data stream; a block interleaver operatively coupled to the first permutation element, to interleave the first permuted data stream to generate an interleaved data stream; and a second permutation element operatively coupled to the block interleaver, to apply a time varying second permutation to the interleaved data stream to generate a second permuted data stream.
 3. The FEC coding system of claim 2, the first permutation element comprising a first plurality of serially coupled permutation stages, and the second permutation element comprising a second plurality of serially coupled permutation stages.
 4. The FEC coding system of claim 3, each of the first plurality of serially coupled permutation stages and the second plurality of serially coupled permutation stages comprising at least one controllable permutation stage, each controllable permutation stage being controllable to select, from a plurality of different permutation maps, a respective permutation map to be applied by each of the at least one controllable permutation stage.
 5. The FEC coding system of claim 4, further comprising: a controller operatively coupled to the at least one controllable permutation stage, to generate a time varying control signal for controlling selection of the respective permutation map to be applied by each of the at least one controllable permutation stage.
 6. The FEC coding system of claim 4, the plurality of different permutation maps comprising pseudo-random permutation maps.
 7. The FEC coding system of claim 6, the block interleaver implementing a matrix transpose to interleave the first permuted data stream.
 8. A transmitter comprising the FEC coding system of claim
 1. 9. A receiver comprising the FEC coding system of claim
 1. 10. The FEC coding system of claim 1, further comprising: an Optical channel Transport Unit (OTUk) frame generator to generate OTUk frames as the data stream, the second error decorrelator comprising a row interleaver operatively coupled to the OTUk frame generator to apply, to data in rows of the generated OTUk frames, the multiple permutation operations in respective different dimensions to generate the permuted data stream; the first error decorrelator comprising a row de-interleaver, the multiple permutation operations in respective different dimensions to apply, to the encoded data stream, the multiple permutation operations to generate the permuted encoded data stream.
 11. The FEC coding system of claim 10, further comprising: an Optical channel Transport Unit (OTUk) framer to delineate OTUk frames from the permuted encoded data stream; the third error decorrelator comprising a row interleaver operatively coupled to the OTUk framer to apply, to data in rows of the delineated OTUk frames, the multiple permutation operations of the third error decorrelator; the fourth error decorrelator comprising a row de-interleaver to apply, to the decoded data stream, the multiple permutation operations of the fourth error decorrelator.
 12. A Forward Error Correction (FEC) coding method comprising: applying multiple permutation operations to a data stream in respective different dimensions to generate a permuted data stream; performing a FEC coding operation, comprising FEC encoding the permuted data stream to generate an encoded data stream; applying, to the encoded data stream associated with the FEC operation, multiple permutation operations in respective different dimensions comprising inverses of the multiple permutation operations applied to the data stream, to generate a permuted encoded data stream; applying multiple permutation operations to the permuted encoded data stream in respective different dimensions to generate a further permuted data stream, the multiple permutation operations applied to the permuted encoded data stream matching multiple permutation operations applied to the data stream; FEC decoding the further permuted data stream to generate a decoded data stream; applying multiple permutation operations to the decoded data stream in respective different dimensions to generate a permuted decoded data stream, the multiple permutation operations applied to the decoded data stream matching the multiple permutation operations applied to the encoded data stream.
 13. The FEC coding method of claim 12, applying multiple permutation operations comprising: applying a time varying first permutation to the encoded data stream to generate a first permuted data stream; block interleaving the first permuted data stream to generate an interleaved data stream; and applying a time varying second permutation to the interleaved data stream to generate a second permuted data stream.
 14. The FEC coding method of claim 13, the applying a time varying first permutation comprising selecting, from a first plurality of different permutation maps, at least one permutation map to be applied to the encoded data stream, and the applying a time varying second permutation comprising selecting, from a second plurality of different permutation maps, at least one permutation map to be applied to the interleaved data stream.
 15. The FEC coding method of claim 12, further comprising: transmitting the permuted encoded data stream.
 16. The FEC coding method of claim 12, further comprising: receiving the encoded data stream.
 17. A communication system comprising: a transmitter comprising: an Optical channel Transport Unit (OTUk) frame generator to generate OTUk frames; a row interleaver operatively coupled to the OTUk frame generator to apply, to data in rows of the generated OTUk frames, multiple permutation operations in respective different dimensions; a Forward Error Correction (FEC) encoder, operatively coupled to the row interleaver, to receive and apply FEC encoding to permuted data from the row interleaver; a row de-interleaver operatively coupled to the FEC encoder to apply, to encoded data from the FEC encoder, multiple permutation operations in respective different dimensions, the multiple permutation operations of the row de-interleaver being inverses of the multiple permutation operations of the row interleaver; and a receiver comprising: an OTUk framer to delineate OTUk frames from signals received from the transmitter over an optical channel; a receiver row interleaver operatively coupled to the OTUk framer to apply, to data in rows of the delineated OTUk frames, multiple permutation operations in respective different dimensions, the multiple permutation operations of the receiver row interleaver matching the multiple permutation operations of the row interleaver; a FEC decoder, operatively coupled to the receiver row interleaver, to receive and apply FEC decoding to permuted data from the receiver row interleaver; a receiver row de-interleaver operatively coupled to the FEC decoder to apply, to decoded data from the FEC decoder, multiple permutation operations in respective different dimensions, the multiple permutation operations of the receiver row de-interleaver matching the multiple permutation operations of the row de-interleaver. 